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Raimund Kirner
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Raimund Kirner is a Principal Lecturer at the
Compiler Technology and Computer Architecure Group
at the
University of Hertfordshire.
Further, I am Adjunct Professor (Habilitation) at the
Institute of Computer Engineering,
Real-Time Systems Group
at the
Vienna University of Technology.
I have studied computer science at the Vienna University of Technology
Dipl.-Ing. (Master's)
degree in 2000.
I received the
Dr.techn. (PhD) degree
at the Vienna University of Technology in 2003 with Peter Puschner as research advisor.
Have a look at
my old homepage
at the Vienna University of Technology.
[ Research ]
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[ Teaching ]
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My research interests include the following topics:
- Parallel Computing
- Parallel computing offers the challenge that the individual jobs
executing in parallel may influence each other, for example, with
regards of extra-functional properties like execution time.
Adequate hardware and software architectures are necessary to bridge
the gap between the many-core computing and embedded computing.
Further, many-core computing also offers to be the base for novel
approaches of robust computing.
In collaboration with Alex Shafarenko I am the local coordinator at UH of the FP7 project
ADVANCE,
where the goal is to use of probabilistic runtime information to
optimize S-Net programs.
This includes program transformations and resource management like
load balancing.
Since 2012 I am the principal investigator at UH of the ARTMIS project
CRAFTERS, where the goal is to develop multi-core systems, including
predictability and reliability.
- Worst-Case Execution Time Analysis
-
The worst-case execution time (WCET) of a program is the maximum
execution time it can take on a concrete target hardware.
The knowledge of the WCET of tasks is crucial for the design of
real-time systems.
Only if safe upper bounds for the WCET of all time-critical tasks
have been established, it becomes possible to verify the
timeliness of the whole real-time system.
Im am the principal investigator of the
FORTAS-rt
project, funded by the
FWF.
In cooperation with the research group of Prof. Helmut Veith, the
reseach of FORTAS-rt focues on measurement-based timing analysis using
efficient automatic generation of test-data.
- Compiler Support for WCET Analysis
- Due to complexity limits and only partially available
system descriptions during the analysis, the calculation of
the WCET requires the provision of additional control flow
information (flow information).
For convenience of the developers the flow facts have to be
provided at source-code level.
But the WCET analysis has to be performed at object-code level to
obtain tight results.
Therefore, it is necessary by the compiler to transform the flow
information from source-code to object-code level.
The flow information has to be transformed in case of control-flow
changing code optimizations performed by the compiler.
I have been principal investigator of the
CoSTA
project, funded by the
FWF.
The research in CoSTA focuses on the generation of predictable code
patterns on processors with timing anomalies and on the
transformation of flow information from source code to object code.
- Predictable Computer Architectures
- WCET analysis is quite complex on modern computer systems.
Modern processors that contains features like pipelines or caches
maintain an internal state to improve peak performance.
Modelling this internal state exactly to calculate a tight WCET
value is often infeasible.
The infeasibility comes from the state explosion due to
input-data-dependent control flow and cache states.
The development of more predictable software and hardware
concepts will reduce the complexity of WCET analysis.
Specific programming paradigms can help to reduce the
complexity of control-flow path analysis.
- Verification of Embedded Systems
- Systematic testing is becoming increasingly important in the
development of embedded systems.
Within our research we focus on techniques to automate the
generation of test cases using formal techniques like model checking.
I have been the local coordinator together with Peter Puschner of the
TeDES
project at the Vienna University of Technology.
Within TeDES, a functional testing framework with automatic test
case generation has been developed.
I have been the principal investigator of the
SECCO
project, funded by the
FWF.
With the SECCO project we initiated the novel field of research on
preserving structural code coverage during code optimization.
Systematic generation of test data at source-code level is especially
useful for embeddedd computing, where portability of development and
verification frameworks is of high importance.
With the work in SECCO we enable code optimization during compilation
while still preserving the structural code coverage initially
achieved by a systematic test-data generation framework at
source-code level.
A prototype implementation based on the GCC compiler has shown that coverage preservation
can be achieved at negligible performance costs, meaning that additional
safety and performance are not contradicting goals.
Presentations available online:
Raimund Kirner is a member of the IEEE Computer Society,
the ACM,
and the Austrian Computer Society (OCG).
Publications and research reports are described in the
publication page.
Information about my teaching activities at the Vienna University
of Technology can be found at
TUWIS
information portal.
- A growing list of links about
computer software and
technology
- The FP7 project ADVANCE
(use of probabilistic runtime information to optimize S-Net programs)
- The coordination language S-Net
(a specification language to describe streaming networks of asynchronous
components separately from the algorithmic specification of the individual
components)
- The SAC compiler
(a compiler for functional array programming for high-performance computing
using the programming language Single Assignment C)
- The FWF FWF project
SECCO
(preservation of structural code coverage metrics during code optimization)
- The FWF FWF project
FORTAS-rt
(a formal timing-analysis framework for real-time systems)
- The FWF FWF project
CoSTA
(compiler-support for timing analysis)
- The Austrian WCET Page
(a good starting point for everyone interested in doing WCET
analysis for real-time systems)
- Calc-WCET
(a tool for static WCET analysis)
- Involvement in Scientific Events (Organization and PC Memberships):
- 12th Intl Workshop on Worst-Case Execution Time Analysis
(WCET'2012),
paper submission deadline: April 20th, 2012
- 7th IEEE International Symposium on Industrial Embedded Systems
(SIES'2012)
- 10th Workshop on Intelligent Solutions in Embedded Systems
(WISES'2012)
- 15th Conference on Design, Automation & Test in Europe
(DATE'2012),
- 6th IEEE International Symposium on Industrial Embedded Systems
(SIES'2011)
- 9th Workshop on Intelligent Solutions in Embedded Systems
(WISES'2011)
- 1st IEEE Workshop on Architectures and Applications for Mixed-Criticality Systems
(AMICS'2011)
- 14th Conference on Design, Automation & Test in Europe
(DATE'2011)
- 4th Int'l ACM Symposium of Applied Computing
(SAC'2011)
Real-Time Systems Track
- 3rd Int'l Workshop on Non-functional System Properties and
Domain Specific Modeling Languages
(NFPinDSML'2010)
- 18th Int'l Conference on Real-Time and Network Systems
(RTNS'2010)
- 10th Int'l Workshop on Worst-Case Execution Time Analysis
(WCET'2010)
- 7th IFIP Working Conference on Distributed and Parallel
Embedded Systems
(DIPES'2010)
- 8th Workshop on Intelligent Solutions in Embedded Systems
(WISES'2010)
- Junior Scientist Conference 2010 at the Vienna University of Technology
(JSC'2010)
- 2nd Int'l Workshop on Non-functional System Properties and
Domain Specific Modeling Languages
(NFPinDSML'2009)
- 15th IEEE Int'l Conference on Embedded and Real-Time Computing Systems
and Applications
(RTCSA'2009)
- 17th International Real-Time and Network Conference
(RTNS'2009)
- 9th Intl Workshop on Worst-Case Execution Time Analysis
(WCET'2009),
Session Chair
- 7th Workshop on Intelligent Solutions in Embedded Systems
(WISES'2009)
- 3rd International Symposium on Leveraging Applications of Formal Methods,
Verification and Validation
(ISOLA'2008),
Track Organizer: Special Track on Non-Functional Requirements in Embedded Systems
- 27th International Symposium on Reliable Distributed Systems
(SRDS'2008)
- 16th International Real-Time and Network Conference
(RTNS'2008)
- 8th Intl Workshop on Worst-Case Execution Time Analysis
(WCET'2008),
PC Chair
- 14th IEEE Int'l Conference on Embedded and Real-Time Computing Systems
and Applications (RTCSA'2008)
- 6th Workshop on Intelligent Solutions in Embedded Systems
(WISES'2008)
- IFIP Working Conference on Distributed and Parallel Embedded Systems
(DIPES'2008)
- 4th Workshop on Dependable Embedded Systems
(WDES'2007)
- 7th Intl Workshop on Worst-Case Execution Time Analysis
(WCET'2007),
Session Chair
- 15th International Real-Time and Network Conference
(RTNS'2007)
-
3rd Workshop on Dependable Embedded Systems
(WDES'2006),
PC Co-Chair
- 4th Intl Workshop on Worst-Case Execution Time Analysis
(WCET'2004),
Session Chair
- 7th IEEE International Symposium on Object-Oriented Real-Time Distributed Computing
(ISORC'2004),
Local Arrangements Chair & Session Chair
- IFIP Working Conference on Distributed and Parallel Embedded Systems
(DIPES'2002),
Session Chair
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This page was last updated on April 5th 2010 by
r.kirner (@) herts.ac.uk